Low Power ASIC Engineer - New College Grad 2027 - CA, Santa Clara, United States
$100,000 - $189,750 USD yearly
Originally posted 13 October 2026 by the employer.
Join NVIDIA’s Low Power DV team to develop GPUs for AI, Automotive, GeForce, and Mobile products.
About the role
This role involves the research and development of energy-efficient GPU and SOC architectures.
What you'll do
- Architect and develop testbench, infrastructure, and testplans to verify power management solutions.
- Bring creative ideas to improve power-aware DV methodologies.
- Influence EDA vendors to improve simulation and debug efficiencies.
What you'll need
- BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
- Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS).
- Understanding of processor architecture and related power management design/DV techniques.
- Experience with Incisive Low-Power or Synopsys VCS NLP.
- Strong debug skills and experience with Verdi.
- Fluent in Verilog, SystemVerilog, and understanding of UVM.
Nice to have
- Prior knowledge of Low Power Architecture, Low Power CV, and deep learning.
- Understanding of power intent in UPF format.
- Background in Low Power architectures or verification.
- Scripting abilities in Python or PERL.
- Knowledge of C or C++.
- Experience writing or maintaining scripts or Makefiles for simulation program builds.
Skills: low power design, power management, testbench, UVM, SystemVerilog, Verilog
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 82 | 1187 |
| Open roles in the wider Digital Design & Verification family | 237 | 3192 · 115 employers |
| Median days open | 56 d | 64 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: low power design, power management, testbench, UVM, SystemVerilog, Verilog
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA (this employer) · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.