Lead Systems Debug Engineer - WA, Bellevue, United States
Originally posted 28 August 2026 by the employer. Relisted by the employer on 5 October 2026.
About the role
What you'll do
- Work on RAS, PCIe, Memory, MCA, CXL, and Micro-Controller related failures with customers.
- Collaborate with AMD global teams to identify solutions.
- Provide validation and debug recommendations to customers.
- Utilize debug tools (e.g., debug scripts, protocol analyzers, SCAN, JTAG tools) to narrow down and root cause customer failures.
- Debug issues found during process, bring-up, validation, and production phases of SOC programs.
- Lead task force and collaborative approaches with multiple teams.
What you'll need
- 10+ years of total experience.
- Experience with RAS (reliability, availability and serviceability) validation and debug.
- Experience with PCIe/CXL functional and protocol (Gen1~Gen6) debug, including IP bring up, validation, and analysis.
- Experience with DDR Memory functional and protocol validation and/or debug.
- Experience with MCA/MCE (Machine check architecture and exception) validation and debug.
- Experience with post silicon validation methodologies.
- Experience with programming languages such as Python, C++, Perl, Ruby.
- Experience with various high-speed test and measurement equipment such as protocol analyzer and scope.
- Experience with X86 micro architecture.
- Bachelors or Masters degree in electrical or computer engineering.
Skills: Systems Debug Engineer, RAS validation, PCIe/CXL debug, DDR Memory validation, Post silicon validation
This role has been open 50 days — slightly above the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
410
|
Median days open
43 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (410 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 58 | 410 |
| Open roles in the wider Silicon Validation & Test family | 150 | 2219 · 113 employers |
| Median days open | 44 d | 43 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Skills observed across this category: Systems Debug Engineer, RAS validation, PCIe/CXL debug, DDR Memory validation, Post silicon validation
Who's hiring in this category
- AMD (this employer) · 58 open roles · median 44 d
- Micron Technology · 39 open roles · median 40 d
- Qualcomm · 36 open roles · median 29 d
- NVIDIA · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 69 d
- Graphcore · 20 open roles · median 122 d
How we counted: 410 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.