Lead Software Engineer - Low Power Verification - San Jose, United States
$114,800 - $213,200 USD yearly
Originally posted 15 September 2026 by the employer.
Help build low-power verification software for Palladium and Protium emulation and prototyping platforms, supporting new IEEE 1801 LRM revisions.
About the role
As a Lead Software Engineer - Low Power Verification, you will be responsible for improving the performance and usability of UPF debug features and adding support for new IEEE 1801 LRM revisions.
What you'll do
- Enhance UPF debug features across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
- Scale UPF event logging and violation detection to capture and report more UPF events for multi-billion-gate low-power designs.
- Rebuild UPF documentation around end-to-end debug scenarios and workflows, with SystemVerilog and UPF examples.
- Develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
- Deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets) with UPF in 2- and 4-state.
- Consolidate and unify UPF debug across Palladium and Protium.
What you'll need
- BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year.
- Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
- Strong debugging skills for root-cause analysis from logs, waveforms, traces, testcases, and user reports.
- Ability to read, review, and reason about C++ code and object-oriented designs.
- Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
Skills: UPF debug, low-power verification, SystemVerilog, C++, AI-assisted debug tools
This role has been open 30 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 155 | 688 |
| Open roles in the wider Physical Implementation family | 178 | 1470 · 108 employers |
| Median days open | 168 d | 78 d (+90 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: UPF debug, low-power verification, SystemVerilog, C++, AI-assisted debug tools
Who's hiring in this category
- Cadence Design Systems (this employer) · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.