Lead Software Engineer - Low-Power Verification - San Jose, United States
$114,800 - $213,200 USD yearly
Originally posted 16 September 2026 by the employer.
About the role
This role involves leading the development of low-power verification software for the Palladium and Protium emulation and prototyping platforms. The focus is on improving UPF compilation performance and correctness, and supporting new IEEE 1801 LRM revisions.
What you'll do
- Contribute to the UPF compilation flow, improving performance, reducing instrumented capacity, and adding self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
- Rebuild UPF documentation around end-to-end compilation workflows with SystemVerilog and UPF examples, ensuring code and documentation synchronization.
- Work with R&D, PE, and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets, each with UPF in 2- and 4-state).
- Help consolidate and unify UPF compilation across Palladium and Protium.
What you'll need
- BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
- Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
- Ability to read, review, and reason about C++ code and object-oriented designs.
- Scripting experience in Perl, Tcl/Tk, and/or Python.
- Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
- Strong technical writing skills to author user guides, specifications, and workflow-first documentation.
Skills: UPF compilation flow, IEEE 1801 UPF, SystemVerilog, C++ code, Palladium and Protium
This role has been open 28 days — below the 34-day median for Software Engineering Semiconductor roles.
Software Engineering Semiconductor · EDA Tools
|
Open roles in category
122
|
Median days open
34 d
|
Median salary
$145k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (122 roles · 28 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 122 |
| Open roles in the wider Software, Firmware & Systems family | 135 | 6119 · 146 employers |
| Median days open | 2 d | 34 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $145k |
Skills observed across this category: UPF compilation flow, IEEE 1801 UPF, SystemVerilog, C++ code, Palladium and Protium
Who's hiring in this category
- Cadence Design Systems (this employer) · 49 open roles · median 2 d
- Renesas Electronics · 13 open roles · median 35 d
- Synopsys · 7 open roles · median 89 d
- Keysight Technologies · 6 open roles · median 146 d
- Intel Corporation · 5 open roles · median 109 d
- KLA Corporation · 5 open roles · median 114 d
How we counted: 122 open Software Engineering Semiconductor (EDA Tools) roles from 28 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.