Lead Logic Design - PCIE IP/Subsystem Engineer - Bengaluru, Karnataka, India
Originally posted 17 September 2026 by the employer — open 0 days.
This role focuses on the development of complex connectivity IP/subsystems.
About the role
This role is for a Lead Logic Design Engineer with expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The position provides technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up for PCIe, CXL, UCIe, Ethernet, and UALink semiconductor-based technologies.
What you'll do
- Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
- Translate specifications and system requirements into robust hardware architecture.
- Design high-performance and scalable logic for controllers/subsystems.
- Develop and review RTL using SystemVerilog/Verilog.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Drive performance, latency, area, and power optimization.
What you'll need
- Extensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.
- Strong RTL design experience using SystemVerilog/Verilog.
- Deep knowledge of PCIe architecture and protocol.
- Strong understanding of high-speed data paths.
- Strong understanding of FIFOs, arbitration, flow control, and error handling.
- Experience with simulation, lint, CDC, synthesis, and timing considerations.
Nice to have
- Experience of working in switching silicon.
- Experience of working on entire cycle from concept to silicon production.
Skills: RTL design, micro-architecture, SystemVerilog, PCIe architecture, high-speed data paths
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
921
|
Median days open
62 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (921 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 921 |
| Open roles in the wider Digital Design & Verification family | 52 | 3004 · 115 employers |
| Median days open | 38 d | 62 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: RTL design, micro-architecture, SystemVerilog, PCIe architecture, high-speed data paths
Who's hiring in this category
- Qualcomm · 134 open roles · median 58 d
- AMD · 60 open roles · median 67 d
- Synopsys · 56 open roles · median 31 d
- NXP Semiconductors · 53 open roles · median 64 d
- NVIDIA · 49 open roles · median 50 d
- Analog Devices · 38 open roles · median 75 d
How we counted: 921 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.