Lead IP Verification Engineer - CA, San Jose, United States
Originally posted 24 September 2026 by the employer.
About the role
As a Lead IP Verification Engineer, you will contribute to FPGA and ASIC solutions. This role focuses on delivering first-pass silicon success for PCIe and CXL-based IP solutions.
What you'll do
- Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
- Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
- Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
- Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
- Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.
What you'll need
- ASIC/IP verification experience using UVM methodology.
- Expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
- Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
- Proficiency in scripting and automation using Python, Perl, or similar languages.
- Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
Nice to have
- Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
- Technical leadership, mentoring experience, and communication skills within geographically distributed teams.
- Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies.
Skills: UVM verification environments, SystemVerilog, PCIe, CXL, high-speed connectivity
This role has been open 16 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1189
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1189 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 102 | 1189 |
| Open roles in the wider Digital Design & Verification family | 265 | 3166 · 114 employers |
| Median days open | 50 d | 64 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM verification environments, SystemVerilog, PCIe, CXL, high-speed connectivity
Who's hiring in this category
- Qualcomm · 106 open roles · median 43 d
- AMD (this employer) · 103 open roles · median 50 d
- NVIDIA · 74 open roles · median 64 d
- Synopsys · 61 open roles · median 26 d
- SiFive · 54 open roles · median 67 d
- Cadence Design Systems · 51 open roles · median 109 d
How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.