Lead I/O Design Engineer - Bangalore, India
Originally posted 17 August 2026 by the employer.
About the role
This role involves designing and validating high-performance I/O circuits for advanced semiconductor SoCs, focusing on developing GPIO, LVDS, DDR, and SerDes support circuits.
What you'll do
- Design and develop custom IO circuits including GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR Interfaces, and high-speed SerDes support circuits.
- Perform transistor-level design and simulation using advanced CMOS technology nodes.
- Develop and optimize ESD protection circuits, Level shifters, Input buffers, Output drivers, and On-chip termination circuits.
- Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
- Perform signal integrity analysis including IBIS model generation, package-aware simulations, crosstalk, and reflection analysis.
- Support silicon bring-up, characterization, debugging, and production ramp activities.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Microelectronics.
- 5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.
- Strong understanding of CMOS device physics, analog circuit design fundamentals, IO architectures, and ESD design methodologies.
- Hands-on experience in custom circuit design using Cadence Virtuoso.
- Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
- Experience with advanced technology nodes (16nm/7nm/5nm preferred).
- Good knowledge of LVS, DRC, EMIR, and reliability checks.
- Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.
Nice to have
- Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.
- Knowledge of package modeling and SI/PI analysis tools.
- Understanding of ESD standards such as HBM, CDM, and IEC.
- Experience in silicon validation and lab characterization.
- Scripting skills in Python, Perl, Tcl, or SKILL.
- Familiarity with IBIS and IBIS-AMI model generation.
- Experience in automotive, AI/ML, networking, mobile, or data center SoCs.
- Exposure to functional safety and reliability requirements.
- Prior ownership of complete IO IP development cycle.
Skills: GPIO, LVDS, DDR, SerDes support circuits, ESD protection, signal integrity analysis
This role has been open 43 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 46 | 1385 · 107 employers |
| Median days open | 43 d | 76 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: GPIO, LVDS, DDR, SerDes support circuits, ESD protection, signal integrity analysis
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.