Lead Functional Product Engineer, Power Analysis - San Jose, United States
$114,800 - $213,200 USD yearly
Originally posted 3 August 2026 by the employer.
Develop and deploy Signoff power analysis flows at customer environments.
About the role
This role involves developing, debugging, and deploying Signoff power analysis flows within customer environments, focusing on power analysis tools.
What you'll do
- Develop and maintain Signoff power analysis flows, integrating with synthesis and PnR stages.
- Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows.
- Deploy and validate power analysis tools at customer sites and provide hands-on technical support.
- Collaborate with customers to optimize power results and improve flow efficiency.
- Contribute to flow automation and scripting for repeatable deployments.
- Document debug findings, best practices, and flow guidelines.
What you'll need
- Hands-on experience with Signoff power analysis (static and dynamic power).
- Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection).
- Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention.
- Proficiency in Verilog/SystemVerilog for design analysis and testcase creation.
- Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs.
- Experience with low-power design methodologies (DVFS, power gating, multi-voltage).
- Familiarity with Liberty (.lib) and SPEF formats.
- Scripting skills: Tcl, Python, or Shell.
- Familiarity with tools such as Joules, Voltus, PTPX or equivalent.
- 3+ years of industry work experience.
Skills: Signoff power analysis, UPF, Verilog/SystemVerilog, low-power design, Joules, Voltus
This role has been open 75 days — slightly above the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
672
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (672 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 672 |
| Open roles in the wider Physical Implementation family | 175 | 1441 · 110 employers |
| Median days open | 171 d | 73 d (+98 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: Signoff power analysis, UPF, Verilog/SystemVerilog, low-power design, Joules, Voltus
Who's hiring in this category
- Cadence Design Systems (this employer) · 153 open roles · median 170 d
- Synopsys · 63 open roles · median 36 d
- Micron Technology · 44 open roles · median 47 d
- Qualcomm · 36 open roles · median 75 d
- GlobalFoundries · 33 open roles · median 38 d
- Keysight Technologies · 32 open roles · median 72 d
How we counted: 672 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.