Lead Full-chip STA and timing signoff Engineer - Bangalore-Technostar B1, India
Originally posted 28 September 2026 by the employer.
About the role
This role involves leading full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs. The work focuses on advanced technology nodes such as 7nm, 5nm, and 3nm.
What you'll do
- Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners.
- Own and drive timing signoff from synthesis to final tapeout.
- Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration.
- Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths.
- Drive MMMC timing methodology and ensure robust timing convergence across PVT corners.
- Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization.
- Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects.
- Lead timing ECO strategies and execute closure with minimal impact to power, area, and performance.
- Collaborate with RTL/design teams to identify architectural or logic changes required for timing improvement.
- Coordinate with IP/block owners for timing budgeting, interface timing closure, and hierarchical timing signoff.
- Ensure signoff quality using industry-standard tools and methodologies.
- Drive correlation between implementation timing and signoff timing.
- Lead tapeout readiness reviews and provide timing risk assessment to program leadership.
- Mentor junior engineers and define best practices for timing methodology and closure.
What you'll need
- Bachelor's or Master's degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering.
- 12+ years of hands-on experience in ASIC/SoC timing analysis and timing closure.
- Strong expertise in full-chip STA and timing signoff for large-scale SoCs.
- Proven experience in advanced technology nodes (such as 7nm, 5nm, 3nm or similar).
- Strong knowledge of synthesis, place-and-route, extraction, and signoff flows.
- Experience with timing budgeting and hierarchical/full-chip integration.
- Solid understanding of clocking architecture, CDC implications, and timing exception handling.
- Ability to debug complex timing issues and drive closure under aggressive schedule targets.
Nice to have
- Strong communication, stakeholder management, and leadership skills.
Skills: full-chip timing closure, STA, timing signoff, MMMC flows, physical design teams
This role has been open 1 day — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
627
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (627 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 43 | 627 |
| Open roles in the wider Physical Implementation family | 70 | 1420 · 109 employers |
| Median days open | 28 d | 64 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: full-chip timing closure, STA, timing signoff, MMMC flows, physical design teams
Who's hiring in this category
- Qualcomm · 114 open roles · median 40 d
- AMD (this employer) · 44 open roles · median 28 d
- Broadcom · 40 open roles · median 78 d
- NVIDIA · 38 open roles · median 53 d
- Synopsys · 27 open roles · median 56 d
- NXP Semiconductors · 25 open roles · median 77 d
How we counted: 627 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.