Lead EDA Software Engineer (C++, Characterization) - San Jose, United States
$136,500 - $253,500 USD yearly
Originally posted 13 April 2026 by the employer.
Develop EDA tools for static and dynamic transistor-level analysis targeting n5 and below.
About the role
Cadence Design Systems is hiring a Lead EDA Software Engineer to develop technologies and products that enable static and dynamic transistor-level analysis of custom digital and mixed-signal circuits. The role focuses on creating frameworks to analyze effects dominant at n5 and below.
What you'll do
- Enhance and expand existing tool architecture to cover timing analysis.
- Create frameworks for analyzing effects dominant at n5 and below.
- Leverage machine learning technology to achieve improvements in speed, capacity, and usability over existing solutions.
What you'll need
- 5+ years of experience in development of EDA tools with expertise in transistor-level timing, power, noise, aging, reliability, or EMIR analysis.
- C++ programming knowledge in a Linux or Unix environment.
- Proficiency in designing data structures, algorithms, and applying software engineering principles.
- Experience developing and maintaining C++ based applications on Unix or Linux platforms.
- Experience with quality and software processes.
- Ability to analyze transistor or gate-level schematics.
Nice to have
- Experience in development of circuit simulation or library characterization programs.
- Understanding of SPICE simulation transistor models at a high level.
- Experience with distributed programming, database design, and cloud APIs for distributed computing.
Skills: C++, characterization, circuit simulation, library characterization, timing analysis, machine learning
This role has been open 215 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 156 | 704 |
| Open roles in the wider Physical Implementation family | 182 | 1513 · 111 employers |
| Median days open | 152 d | 70 d (+82 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: C++, characterization, circuit simulation, library characterization, timing analysis, machine learning
Who's hiring in this category
- Cadence Design Systems (this employer) · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology · 45 open roles · median 55 d
- GlobalFoundries · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.