Lead Design Verification Engineer-Memory Controller - CA, San Jose, United States
Originally posted 22 September 2026 by the employer.
Verify DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC).
About the role
This role involves providing technical leadership and expertise in the verification of DRAM Memory Controller IPs, high-speed Crypto, and Network-on-Chip (NoC). The focus includes architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level for first-pass silicon success.
What you'll do
- Lead verification of high-speed Crypto, Network-on-Chip (NoC), and DRAM Memory controller (DDR5, LPDDR6, HBM4) designs. - Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. - Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. - Develop and execute comprehensive verification plans, including testbenches and test cases. - Collaborate with design, architecture, and software teams to define and implement verification strategies. - Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
What you'll need
- Hands-on experience with verification of memory controllers such as DDR, LPDDR, and HBM. - Strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling. - Proven track record in technical leadership of teams with 5+ engineers, including planning, execution, tracking, verification closure, and delivery to programs. - Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. - BS with 8+ years, MS with 6+ years, or PhD with 3+ years in Electrical Engineering, Computer Engineering, or Computer Science.
Nice to have
- Experience as a verification architect, establishing the verification methodology, tools, and infrastructure for high-performance IP and/or VLSI designs. - Familiarity with verification management tools and database management for regression. - Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor). - Experience with gate-level simulation, power-aware verification. - Experience with silicon debug at the tester and board level.
Skills: DRAM Memory Controller IPs, UVM, System Verilog, formal verification, testbenches
This role has been open 19 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1183
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1183 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 102 | 1183 |
| Open roles in the wider Digital Design & Verification family | 265 | 3171 · 114 employers |
| Median days open | 51 d | 64 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: DRAM Memory Controller IPs, UVM, System Verilog, formal verification, testbenches
Who's hiring in this category
- Qualcomm · 105 open roles · median 44 d
- AMD (this employer) · 102 open roles · median 51 d
- NVIDIA · 73 open roles · median 65 d
- Synopsys · 61 open roles · median 27 d
- SiFive · 54 open roles · median 68 d
- Cadence Design Systems · 51 open roles · median 110 d
How we counted: 1183 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.