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Analog Devices

Lead Design Evaluation Engineer - Hyderabad, India

Analog Devices India, Hyderabad, India 12 days ago
Verification, Validation & Test

Originally posted 23 September 2026 by the employer.

About the role

This role involves leading the definition and execution of evaluation strategies for FPGA prototypes and automotive networking ASICs.

What you'll do

  • Define and lead evaluation strategies, test plans, and methodologies for FPGA prototypes and automotive networking ASICs.
  • Develop, bring up, and maintain hardware and software evaluation platforms, test fixtures, and reference systems.
  • Develop modular, maintainable test and automation software in C and Python.
  • Execute and analyse complex silicon and FPGA test cases; debug failures across hardware, firmware, software, interfaces, and system boundaries.
  • Perform electrical and functional measurements using oscilloscopes, logic analysers, protocol analysers, signal generators, and power supplies.
  • Evaluate Automotive Ethernet T1S and related networking functionality.

What you'll need

  • Seven or more years of relevant experience in design evaluation, silicon validation, product engineering, or systems engineering.
  • Demonstrated experience evaluating FPGA prototypes and performing bench validation or characterisation of ASICs.
  • Strong proficiency in C and Python.
  • Strong knowledge of embedded systems, digital hardware, laboratory measurement techniques, and hardware/software integration.
  • Proven ability to diagnose complex problems using structured debugging and root-cause analysis.
  • Working knowledge of Ethernet and networking concepts, together with experience using serial interfaces such as SPI, I²C, and UART.

Nice to have

  • Experience with automotive Ethernet technologies, including 10BASE-T1S, single-pair Ethernet, MAC-PHY devices, or Physical Layer Collision Avoidance.
  • Familiarity with automotive networking architectures, zonal systems, or software-defined vehicles.
  • Experience with Ethernet protocol analysis, network traffic generation, performance measurement, interoperability testing, or fault injection.
  • Experience developing embedded firmware for microcontrollers and integrating host-side software with evaluation hardware.
  • Experience with audio and video interfaces or data paths, including PDM and RGB8.
  • Familiarity with source control, continuous integration, automated regression frameworks, requirements traceability, and issue-tracking systems.

Skills: FPGA prototypes, automotive networking ASICs, system-level validation, characterisation, lab expertise, test automation

Market context

This role has been open 0 days — well below the 51-day median for Post-Silicon Validation roles.

Post-Silicon Validation · Silicon Validation

Open roles in category
327
Median days open
51 d
Median salary
$166k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Analog Devices compares in Post-Silicon Validation hiring
Metric Analog Devices All employers we track in this specialty (327 roles · 62 employers)
Open roles in this specialty 15 327
Open roles in the wider Silicon Validation & Test family 79 2111 · 111 employers
Median days open 7 d 51 d (−44 d vs this employer)
Median salary (USD postings) — $166k

Skills observed across this category: FPGA prototypes, automotive networking ASICs, system-level validation, characterisation, lab expertise, test automation

Who's hiring in this category

  • AMD · 50 open roles · median 48 d
  • Micron Technology · 29 open roles · median 25 d
  • Qualcomm · 25 open roles · median 83 d
  • Graphcore · 19 open roles · median 98 d
  • Microchip Technology · 18 open roles · median 51 d
  • NVIDIA · 17 open roles · median 19 d

How we counted: 327 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

Apply now
India, Hyderabad, India
On-site
12 days ago

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