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Cadence Design Systems

Lead Design Engineer ( Synthesis/LEC/CLP ) - India

Cadence Design Systems 2 Locations, India 20 days ago
Physical Design & EDA

Originally posted 15 September 2026 by the employer — open 4 days.

About the role

This role involves hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs.

What you'll do

  • Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches.
  • Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues.
  • Support CLP flows.
  • Write and maintain ECO scripts and timing/power constraints for design blocks.
  • Independently triage and document issues, escalating complex or systemic issues as needed.
  • Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure.

What you'll need

  • 5–8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows.
  • Working knowledge of Cadence Genus and Conformal (LEC and/or CLP).
  • Familiarity with UPF/CPF-based power intent (IEEE 1801).
  • Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.
  • Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts.

Skills: Synthesis, LEC, CLP, UPF/power-intent, Genus, Conformal

Market context

This role has been open 4 days — well below the 59-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
604
Median days open
59 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Cadence Design Systems compares in Physical Design hiring
Metric Cadence Design Systems All employers we track in this specialty (604 roles · 79 employers)
Open roles in this specialty 21 604
Open roles in the wider Physical Implementation family 198 1373 · 107 employers
Median days open 89 d 59 d (+30 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: Synthesis, LEC, CLP, UPF/power-intent, Genus, Conformal

Who's hiring in this category

  • Qualcomm · 108 open roles · median 42 d
  • NVIDIA · 39 open roles · median 44 d
  • Broadcom · 38 open roles · median 69 d
  • AMD · 35 open roles · median 39 d
  • Synopsys · 27 open roles · median 58 d
  • Renesas Electronics · 25 open roles · median 46 d

How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
2 Locations, India
On-site
20 days ago

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