Lead CPU Power and Performance Architect - CA, Santa Clara, United States
Originally posted 30 July 2026 by the employer.
This role focuses on CPU Core & Cache complexes.
About the role
This role is for a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meet performance requirements within reliability and system platform constraints. This involves a technical leadership role focused on interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, as well as the package and platform impact to the power delivery network and thermal management.
What you'll do
- Align product requirements with CPU IP by defining usage models and operating conditions.
- Drive alignment on power delivery architecture, packaging infrastructure, and platform definition.
- Drive alignment on thermal modeling, packaging, and platform definition.
- Translate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.
- Lead technical reviews across SoC architecture, physical design implementation, package design, and platform definition.
- Partner with power and performance modeling teams to align assumptions and drive architecture decisions.
What you'll need
- Strong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system-driven constraints.
- Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting).
- Working knowledge of device and system reliability requirements and thermal management algorithms.
- Demonstrated ability to lead complex cross-functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform).
- Familiarity collaborating with pre-silicon power & performance modeling teams.
- Experience with program milestone readiness.
Skills: CPU Core & Cache, PPA Architect, power delivery network, thermal management, SoC architecture
This role has been open 80 days — slightly above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
79 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 472 |
| Open roles in the wider Digital Design & Verification family | 251 | 3201 · 115 employers |
| Median days open | 61 d | 79 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: CPU Core & Cache, PPA Architect, power delivery network, thermal management, SoC architecture
Who's hiring in this category
- Qualcomm · 73 open roles · median 88 d
- NVIDIA · 56 open roles · median 71 d
- Apple · 36 open roles · median 12 d
- AMD (this employer) · 34 open roles · median 60 d
- Arm Holdings · 27 open roles · median 115 d
- Micron Technology · 22 open roles · median 107 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.