Lead ASIC Modem Design Engineer, Satellite Communication
Define and implement digital SoC modems and DSP data path subsystems in SystemVerilog for Low Earth Orbit satellite communications.
About the role
As a Lead ASIC Modem Design Engineer, you will define and implement digital SoC modems for communications via Low Earth Orbit satellites and Amazon gateways. The role spans wireless system architecture translation to microarchitecture, RTL implementation, timing and power optimization, and chip-level validation.
What you'll do
- Define specifications and microarchitecture for modem PHY subsystem blocks, including signal processing data paths.
- Lead the design of one or more DSP data path subsystems in SystemVerilog while interpreting reference models in MATLAB, C, or C++.
- Implement control plane logic design and interfaces to bus fabrics.
- Create standalone testbenches to verify block correctness, and participate in system-level verification using UVM, SystemC, and DPI-C.
- Work closely with implementation teams to ensure blocks meet DFT, timing, and power targets.
- Support emulation platforms for early software development and system-level validation of modem IP.
What you'll need
- Experience implementing wireless system architecture in silicon from specification to microarchitecture, RTL design, and chip-level validation.
- Demonstrated experience in SystemVerilog RTL design for DSP data path subsystems and control plane logic.
- Ability to interpret and work from reference models written in MATLAB, C, or C++.
- Experience constructing or working with verification testbenches utilizing UVM, SystemC, or DPI-C.
- Working knowledge of DFT, timing closure, power optimization, and hardware-software integration across PHY-MAC boundaries.
- Compliance with export control requirements (U.S. citizen, U.S. national, lawful permanent resident, refugee, or asylee).
Skills: RTL, SystemVerilog, DSP, MATLAB, modem PHY, microarchitecture
More semiconductor jobs: RTL design jobs · San Diego jobs
This role has been open 0 days — well below the 102-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
|
Open roles in category
34
|
Median days open
102 d
|
Category median salary (all employers)
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (34 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 34 |
| Open roles in the wider Digital Design & Verification family | 24 | 3381 · 114 employers |
| Median days open | 0 d | 102 d (−102 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: RTL, SystemVerilog, DSP, MATLAB, modem PHY, microarchitecture
Who's hiring in this category
- Infineon Technologies · 5 open roles · median 33 d
- Celero · 4 open roles · median 11 d
- Keysight Technologies · 4 open roles · median 125 d
- Altera · 2 open roles · median 43 d
- AMD · 2 open roles · median 21 d
- Marvell Technology · 2 open roles · median 163 d
How we counted: 34 open Digital/RTL Design (Mixed Signal DSP) roles from 18 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.