Lead ASIC Design Engineer
$143,800 - $230,000 USD yearly
Originally posted 19 June 2026 by the employer.
About the role
Broadcom is seeking a Lead ASIC Design Engineer to serve as the Chip Lead responsible for top-level architecture, microarchitecture, and full chip integration. You will own the design outcome end-to-end from early product definition through foundry tape-out.
What you'll do
- Define top-level digital architecture, partition hard and soft IP blocks, and direct full chip integration. - Author, optimize, and maintain synthesizable SystemVerilog/Verilog RTL for digital blocks, control logic, clocking structures, and register files (CSRs). - Align cross-disciplinary teams spanning logic design, physical design, architecture, and verification to hit target power, performance, and area (PPA) metrics. - Drive top-level chip timing constraints (SDC), establish block-level timing budgets, and define clock domain crossing (CDC) strategies. - Execute front-end logic synthesis, static timing analysis (STA), static quality checks (Lint, SpyGlass, JasperGold CDC), and manage integration of analog macros and third-party IP. - Own the final tape-out sign-off checklist and collaborate with post-silicon validation and software teams during chip bring-up and lab debug.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 12+ years of direct industry experience in ASIC/SoC digital design, including a track record serving as a design lead or chip lead. - Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles. - Experience with front-end EDA tools for synthesis, static timing analysis (STA), and CDC analysis (Synopsys or Cadence tool suites). - A track record of successful, first-pass silicon tape-outs on modern process technologies. - Legal authorization to work in the US.
Nice to have
- Experience with mixed-signal or high-speed PHY-adjacent architectures such as SerDes, PCIe, DDR, or custom interconnects. - Familiarity with DFT planning, including scan insertion, ATPG planning, and boundary scan. - Proficiency in scripting with Python, Tcl, or Perl to automate front-end design flows.
Skills: RTL Design, chip lead, microarchitecture, integration, tape-out
This role has been open 125 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 1078 |
| Open roles in the wider Digital Design & Verification family | 52 | 3297 · 115 employers |
| Median days open | 89 d | 63 d (+26 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL Design, chip lead, microarchitecture, integration, tape-out
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.