Lead Analog Layout Design Engineer (SerDes) - CORK 01, Ireland
Analog & Mixed-Signal Design
Originally posted 20 May 2026 by the employer — open 112 days. Relisted by the employer on 28 August 2026.
About the role
This role involves technical leadership within a custom layout design team, focusing on high-speed SerDes for UCIe products.
What you'll do
2nm FinFET CMOS).
- Design quality layouts of analog/mixed-signal circuit blocks in collaboration with circuit designers.
- Execute all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules.
- Provide technical leadership in layout design from block level to PHY top level integration and sign off.
- Collaborate with global teams working in different time zones.
What you'll need
- Minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC layout design and development.
- Proficient layout design experience in SerDes circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators.
- Experience implementing high speed and high accuracy cells, blocks and IP blocks.
- Experience working with custom layout designers to build high quality IP and test chips.
- Experience working with circuit designers and project managers.
- BEng, MEng or PhD.
Skills: custom transistor-level layout, SerDes, PLLs, CDR, DRC, LVS
Market context
This role has been open 114 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: custom transistor-level layout, SerDes, PLLs, CDR, DRC, LVS
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.