Lead Analog IC Design Engineer - San Jose, United States
$119,000 - $221,000 USD yearly
Originally posted 30 September 2026 by the employer.
This role focuses on designing CMOS SerDes and high-speed I/O integrated circuits.
About the role
This role involves designing and developing analog and mixed-signal circuits from initial concept through final verification to ensure conformance with customer requirements.
What you'll do
- Design and develop analog and mixed-signal circuits. - Ensure conformance with customer requirements through final verification. - Utilize CAD tools for circuit simulation, layout, and physical verification.
What you'll need
- At least three years of experience designing and developing CMOS SerDes or high-speed I/O integrated circuits. - Design experience with transmitters and receivers, serializers and deserializers, phase interpolators, low-jitter PLLs, high-speed clock-distribution circuits, bias circuits, and voltage regulators. - Understanding of jitter and signal-equalization techniques. - Proficiency with CAD tools for circuit simulation, layout, and physical verification. - Master’s degree or Ph.D. in electrical engineering.
Nice to have
- Working knowledge of common SerDes standards and their electrical requirements. - Experience with Cadence design tools and laboratory testing. - Design experience at data rates above 10 Gbps and in process technologies below 28 nm.
Skills: CMOS SerDes, high-speed I/O, transmitters and receivers, PLLs, jitter and signal-equalization
This role has been open 9 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
76 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (244 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 27 | 1416 · 106 employers |
| Median days open | 182 d | 76 d (+106 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: CMOS SerDes, high-speed I/O, transmitters and receivers, PLLs, jitter and signal-equalization
Who's hiring in this category
- AMD · 32 open roles · median 36 d
- Synopsys · 29 open roles · median 24 d
- Cadence Design Systems (this employer) · 19 open roles · median 182 d
- Qualcomm · 18 open roles · median 60 d
- Micron Technology · 13 open roles · median 69 d
- Apple · 12 open roles · median 10 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.
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