Layout Engineer - Bengaluru, Karnataka, India
Originally posted 24 August 2026 by the employer.
About the role
This senior Layout Engineer role involves leading layout activities for projects and collaborating with design, packaging, and process teams.
What you'll do
- Frame layout schedules, effort estimation, and risk mitigation plans for layout activities.
- Understand IC architecture and requirements by working with designers.
- Balance area, performance, and schedule during layout development.
- Work with the Process development team on PDK, P-cell, and Design rule updates.
- Analyze and close Electro Migration, Thermal gradients, ESD/LU performance, and layout parasitics.
- Mentor junior layout engineers, review work, and provide feedback.
What you'll need
- Full chip layout experience from definition through release to production.
- Strong LVS, DRC, ERC, and antenna debug skills.
- Proficient in analog and mixed-signal layout techniques and verification processes including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques.
- Good understanding of all layout parasitics (R, C, diodes, BJTs).
- Good understanding of device physics and semiconductor fabrication process.
- Experience with 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD technologies.
- Well versed with tools such as Virtuoso XL/Assura /PVS/Voltas.
Skills: Full chip layout, LVS, DRC, ERC, analog and mixed-signal layout, Virtuoso XL/Assura /PVS/Voltas, PDK, P-cell
This role has been open 36 days — well above the 25-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
49
|
Median days open
25 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 49 |
| Open roles in the wider Analog & Mixed-Signal family | 58 | 1385 · 107 employers |
| Median days open | 42 d | 25 d (+17 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Full chip layout, LVS, DRC, ERC, analog and mixed-signal layout, Virtuoso XL/Assura /PVS/Voltas, PDK, P-cell
Who's hiring in this category
- Celero · 8 open roles · median 32 d
- Analog Devices · 7 open roles · median 12 d
- Marvell Technology · 4 open roles · median 16 d
- Broadcom · 3 open roles · median 8 d
- onsemi · 3 open roles · median 35 d
- QORVO · 3 open roles · median 33 d
How we counted: 49 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.