Layout Design, Sr Staff Engineer
Originally posted 19 August 2026 by the employer.
About the role
This Senior Staff Engineer role involves leading the complete physical layout development for advanced memory IP, including SRAM, ROM, and eDRAM. The position focuses on shaping layout methodologies and automation strategies across Synopsys' memory product lines.
What you'll do
- Lead complete physical layout development for advanced memory IP including SRAM, ROM, eDRAM, and emerging memory types across nodes from 3nm to mature technologies.
- Define and implement layout methodologies that improve area efficiency, performance, power consumption, and manufacturability.
- Resolve complex DRC, LVS, ERC, and EMIR issues in dense memory structures, ensuring first-pass silicon success.
- Lead RC extraction, parasitic analysis, and signal integrity optimization efforts, collaborating with circuit designers.
- Develop layout automation, generators, validation flows, and productivity tools using scripting languages.
- Mentor staff and senior layout engineers across multiple projects and sites, providing technical guidance and reviewing critical design decisions.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related technical discipline.
- 10+ years of hands-on experience in custom physical layout design with deep expertise in advanced memory IP development.
- Demonstrated success delivering memory IP across multiple advanced technology nodes and tapeouts, including SRAM, ROM, or eDRAM in production silicon.
- Deep expertise in memory layout including bit-cell design, array structures, sense amplifiers, decoders, redundancy circuits, I/O, and peripheral blocks.
- Strong proficiency with layout tools such as Synopsys Custom Compiler, Cadence Virtuoso, or equivalent custom design platforms.
- Advanced understanding of foundry design rules, DRC/LVS closure methodologies, reliability requirements, EMIR validation, and memory-specific constraints.
Skills: memory layout, SRAM bit-cells, DRC/LVS, RC extraction, layout automation, Cadence Virtuoso
This role has been open 45 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: memory layout, SRAM bit-cells, DRC/LVS, RC extraction, layout automation, Cadence Virtuoso
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.