Layout Design, Sr Engineer in Etown Tan Binh
Originally posted 6 July 2026 by the employer.
About the role
This role involves translating circuit concepts into physical silicon, making decisions that affect performance, power, and manufacturability. You will work on Foundation IP that powers chips across the industry.
What you'll do
- Design and develop custom layouts for Embedded Memory IPs, Standard Cells, and IO structures.
- Optimize layout topologies for density, performance, power, and manufacturability across advanced process nodes.
- Collaborate with circuit designers and verification teams to ensure layouts meet electrical and physical design requirements.
- Debug and resolve DRC, LVS, and antenna violations in complex hierarchical designs.
- Develop and refine layout methodologies and automation flows to improve efficiency.
- Participate in design reviews and provide technical feedback on layout strategies.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related field.
- 2+ years of hands-on experience in custom IC layout design, with focus on memory compilers, standard cells, or analog/mixed-signal blocks.
- Deep understanding of layout fundamentals including device matching, parasitic extraction, electromigration, and IR drop.
- Proficiency with industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent.
- Solid grasp of DRC/LVS verification flows and ability to debug complex rule violations.
Skills: custom layout, Embedded Memory IPs, DRC/LVS, Cadence Virtuoso, physical silicon
This role has been open 89 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: custom layout, Embedded Memory IPs, DRC/LVS, Cadence Virtuoso, physical silicon
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.