Layout Design, Senior / Staff Engineer - 18157
Originally posted 16 August 2026 by the employer.
About the role
This role involves custom layout design for memory leafcells and standard cells, optimizing performance, area, and power across FinFET nodes using Custom Compiler and ICV tools.
What you'll do
- Design custom layouts for memory leafcells and standard cells, optimizing for performance, area, and power across FinFET nodes.
- Run physical verification flows including DRC, LVS, and ERC using ICV tools, debugging violations and ensuring clean signoff.
- Collaborate with circuit designers to translate schematics into layouts that meet electrical specifications and design intent.
- Develop automation scripts in Perl, Shell, or TCL to streamline layout tasks and verification flows.
- Optimize existing layouts for speed, area, or power based on performance analysis and downstream feedback.
- Participate in design reviews, providing layout feasibility input and identifying potential issues early.
What you'll need
- 2+ years of hands-on experience in custom layout design with standard cells, memory blocks, or analog/mixed-signal circuits.
- Deep familiarity with FinFET technology nodes and advanced process design challenges.
- Proficiency with Custom Compiler and ICV for layout and physical verification.
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field.
- Ability to write and debug scripts in Perl, Shell, or TCL to automate layout and verification tasks.
Skills: custom layout design, memory leafcells, standard cells, FinFET, DRC/LVS
This role has been open 49 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: custom layout design, memory leafcells, standard cells, FinFET, DRC/LVS
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.