Kernel Engineer (Custom Silicon), Hardware - Palo Alto, CA
$200,000 - $420,000 USD yearly
Originally posted 28 June 2026 by the employer.
About the role
This role designs and implements kernel generators that programmatically emit optimized low-level assembly code for custom silicon. You will optimize deep learning operations, including GEMMs, FlashAttention, and custom activations, for hardware architecture efficiency.
What you'll do
- Design and build C++ code-generation frameworks and meta-programming toolchains that automatically emit optimized custom ISA assembly code. - Author and optimize core deep learning primitives (GEMM/MatMul, Attention mechanisms, Convolutions, and element-wise layers) directly targeted at custom hardware. - Hand-craft and automate instruction scheduling, register allocation, and software pipelining to maximize ALU utilization and hide execution latency. - Design tiling, double-buffering, and data-movement strategies to optimize on-chip SRAM utilization and minimize memory bandwidth bottlenecks. - Partner with RTL and architecture teams to evaluate hardware simulations, provide feedback on the ISA, and influence the design of future compute units. - Benchmark generated assembly against hardware simulators and silicon using hardware performance counters to validate performance and mathematical correctness.
What you'll need
- Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field, with 5+ years of practical industry experience in low-level performance programming. - Understanding of hardware programming models (such as CUDA, Triton, CUTLASS, or custom accelerator assembly) and a track record of shipping optimized kernels. - Knowledge of computer architecture, including vector units, execution pipelines, register files, and memory hierarchies (caches, SRAM, HBM/DRAM). - Proficiency in modern C++ for building meta-programming and code-generation frameworks. - Mathematical foundation in linear algebra operations and deep learning primitives.
Nice to have
- Experience implementing microarchitectural optimizations for Tensor Cores, matrix multiply-accumulate units, or custom vector extensions. - Experience utilizing advanced C++ template metaprogramming or code-generation techniques to automate the creation of heavily parameterized kernel variants. - Experience with low-level hardware profiling tools, execution tracing, and utilizing performance counters to identify cache misses, pipeline stalls, and ALU bubbles.
This role has been open 114 days — well above the 62-day median for Systems Software Engineering roles.
Systems Software Engineering · Systems Software
|
Open roles in category
698
|
Median days open
62 d
|
Median salary
$209k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | River | All employers we track in this specialty (698 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 698 |
| Open roles in the wider Software, Firmware & Systems family | 7 | 6296 · 145 employers |
| Median days open | 114 d | 62 d (+52 d vs this employer) |
| Median salary (USD postings) | — | $209k |
Who's hiring in this category
- Qualcomm · 174 open roles · median 79 d
- NVIDIA · 136 open roles · median 43 d
- AMD · 62 open roles · median 51 d
- Broadcom · 22 open roles · median 58 d
- Mobileye · 21 open roles · median 91 d
- Arm Holdings · 20 open roles · median 119 d
How we counted: 698 open Systems Software Engineering (Systems Software) roles from 73 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.