Jr. FPGA Developer (Compute Test, North Reading)
$98,700 - $157,900 USD yearly
Originally posted 24 September 2026 by the employer.
Develop advanced test solutions for high-performance SoCs and accelerators.
About the role
This role supports the design and delivery of high-performance FPGA-based solutions for advanced test solutions in the Compute Test Division. It focuses on the intersection of FPGA design, board-level hardware, and system architecture, working with high-speed interfaces, complex digital systems, and system-level constraints.
What you'll do
- Support FPGA design implementation and bring-up under guidance. - Develop FPGA logic for defined interfaces and subsystems. - Collaborate with hardware, software, systems, and design verification teams on system-level solutions. - Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation. - Build and maintain TCL and Python scripts for design and validation workflows. - Partner in code reviews, design discussions, and PCB and system design decisions affecting FPGA performance.
What you'll need
- 2+ years of hands-on experience in FPGA design and development. - Working knowledge of Verilog/SystemVerilog for design and debugging. - Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure. - Understanding of digital design fundamentals and the ability to interpret schematics. - Exposure to high-speed interfaces such as PCIe, DDR, SerDes, and familiarity with protocols such as AXI4, USB, I2C, and SPI. - Basic experience bringing up or debugging FPGA designs on hardware platforms. - Basic TCL and Python scripting skills and experience with version control systems.
Nice to have
- Coursework or project experience with SystemVerilog-based verification methodologies such as UVM. - Familiarity with FPGA SoCs and embedded processor subsystems. - Exposure to ATE or measurement equipment design. - Basic understanding of signal integrity and high-speed serial interfaces. - Familiarity with AI tools for engineering design.
This role has been open 22 days — well below the 60-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
102
|
Median days open
60 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (102 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 102 |
| Median days open | 70 d | 60 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera · 30 open roles · median 59 d
- AMD · 12 open roles · median 50 d
- Teradyne (this employer) · 10 open roles · median 69 d
- Qualcomm · 8 open roles · median 41 d
- Microchip Technology · 6 open roles · median 92 d
- Infineon Technologies · 4 open roles · median 37 d
How we counted: 102 open FPGA Design (RTL Design) roles from 26 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.