[Japan] Design Verification Engineer - Remote
Verify AI SoC architectures powered by the Dynamic Neural Accelerator AI processor IP.
About the role
As a Design Verification Engineer on the Artificial Intelligence Hardware Accelerator Team, you will collaborate with design and architecture teams to build verification environments for AI SoCs. You will contribute to IP, performance, and SoC-level verification using the Dynamic Neural Accelerator AI processor IP.
What you'll do
- Build and maintain verification infrastructure, including VIPs, memory models, monitors, and configurable testbenches in SystemVerilog/UVM. - Write and debug SystemVerilog assertions and develop automated testbenches. - Define functional coverage and execute overall functional and code coverage analysis. - Execute ASIC power estimation and power-aware verification. - Automate tool flows and generate verification result reports. - Support gate level simulations and delay modeling across blocks and systems.
What you'll need
- 6-7 years of functional verification experience targeting blocks and systems using SystemVerilog/UVM. - Demonstrated experience building complete verification infrastructure from scratch. - Experience with coverage-driven verification, metric-driven verification, and constraint random verification. - Experience verifying systems featuring high-speed buses such as AXI4. - Hands-on experience with gate level simulations, delay modeling, and debugging RTL and testbenches. - Direct experience writing and maintaining SystemVerilog assertions and functional coverage models.
Nice to have
- Prior experience working with VIPs and verifying IPs or systems using PCIe or DDR protocols. - Experience with SoC-level verification. - Experience using Continuous Integration tools such as Jenkins, Gitlab CI, or Circle CI. - Experience with synthesis (Cadence Genus), power analysis (Cadence Joules), or equivalence checking (Cadence Conformal). - Prior experience working with standard cell libraries. - Scripting experience with Perl or Python.
Skills: SystemVerilog/UVM, functional verification, assertions, coverage-driven verification, gate level simulations
This role has been open 124 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1268 |
| Open roles in the wider Digital Design & Verification family | 8 | 3359 · 116 employers |
| Median days open | 124 d | 67 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog/UVM, functional verification, assertions, coverage-driven verification, gate level simulations
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.