Design and automate DPU IPs across ASIC and FPGA platforms using Verilog, SystemVerilog, and High-Level Synthesis.
About the role
MangoBoost is recruiting IP Design Engineers across Digital Hardware IP Design and Design Technology tracks to develop hardware designs targeting both ASIC and FPGA platforms. The role spans architecture design, RTL implementation, and design flow automation for DPU IPs.
What you'll do
- Develop IPs for FPGA and ASIC implementation with a focus on power, performance, and area (PPA).
- Establish and maintain IP design, delivery, quality assurance, and SoC integration flows.
- Implement DPU IPs in Verilog, SystemVerilog, or SystemC, or build automation scripts (Python, Perl) for EDA workflows.
- Collaborate with cross-functional architecture, verification, SoC design, and software teams for integration and validation.
- Interface with EDA vendors to evaluate tool versions and assess emerging methodologies.
What you'll need
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Minimum 3 years of industry experience in hardware design within ASIC or FPGA design environments.
- Solid understanding of digital hardware design concepts and SoC or FPGA development flows.
- Hands-on experience with Verilog HDL and industry-standard EDA tools.
Nice to have
- Experience with network or high-speed interface IPs such as Ethernet, PCIe, or UCIe.
- Experience with storage-related IPs such as SSD controller design.
- Experience with High-Level Synthesis tools including Catapult HLS or Stratus.
- Experience with top-level SoC integration and end-to-end design flows spanning RTL, DV, and backend implementation.
- Experience with scripting and automation for design workflows, including RTL code transformation/generation and memory model replacement.
- Experience managing standard cell libraries, memory models, and hard macro IPs, and setting up QA flows including linting, CDC, synthesizability, and RTL-level power estimation.
Skills: Verilog, SystemVerilog, RTL, DPU, EDA
More semiconductor jobs: RTL design jobs · South Korea jobs
First seen in our index 3 days ago, well below the 65-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1098
|
Median days since first seen
65 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MangoBoost | All employers we track in this specialty (1098 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1098 |
| Open roles in the wider Digital Design & Verification family | 3 | 3499 · 119 employers |
| Median days since first seen | 3 d | 65 d (+62 d vs this employer) |
| Median salary (USD postings) | n/a | $188k |
Skills observed across this category: Verilog, SystemVerilog, RTL, DPU, EDA
Who's hiring in this category
- Qualcomm · 142 open roles · median 74 d
- AMD · 92 open roles · median 55 d
- Synopsys · 89 open roles · median 54 d
- NVIDIA · 48 open roles · median 67 d
- NXP Semiconductors · 45 open roles · median 110 d
- Analog Devices · 40 open roles · median 57 d
How we counted: 1098 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.