Internship - PDK Engineer - Lexington, KY
Originally posted 21 September 2026 by the employer — open 0 days.
About the role
This internship focuses on developing and improving parameterized cells (Pcells) and creating/maintaining verification rule decks within the PDK (Process Design Kit) development team.
What you'll do
- Develop and improve parameterized cells (Pcells) for devices like FETs, BJT, diode, and passive components.
- Author and maintain Calibre DRC, LVS, RCX, and Latchup rule decks.
- Implement and execute formal QA procedures for DRC/LVS/RCX rule decks and PDK deliverables.
- Configure techfiles, rule decks, and verification scripts for Cadence and Mentor flows and major EDA tools.
- Create and maintain automation scripts using Python, TCL, SKILL, Ruby, or Bash to support PDK build and release processes.
- Respond to design center requests, troubleshoot PDK issues, and support PDK users.
What you'll need
- Working toward a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline.
- Experience writing automation and EDA scripts in Python, TCL, SKILL, Ruby, or Bash.
- Familiarity with Cadence and Mentor design environments and Calibre verification tools such as DRC, LVS, PERC, and QRC.
- Understanding of semiconductor device structure, VLSI concepts, IC design flow, and front-to-back layout practices.
- Exposure to layout verification and physical verification concepts and tools.
- Basic experience with UNIX/Linux environments and MS Office.
This role has been open 0 days — well below the 87-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
87 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (671 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 671 |
| Open roles in the wider Physical Implementation family | 32 | 1382 · 107 employers |
| Median days open | 66 d | 87 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 146 d
- Synopsys · 55 open roles · median 60 d
- NVIDIA · 46 open roles · median 65 d
- Micron Technology · 35 open roles · median 122 d
- Qualcomm · 34 open roles · median 73 d
- Intel Corporation · 29 open roles · median 26 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.