Intern - Next Gen HBM Platform Arch - Folsom, CA, United States
$50 - $50 USD hourly
Originally posted 5 October 2026 by the employer.
HBM Platform Architecture
About the role
This role involves contributing to the development of future HBM platforms by evaluating electrical, thermal, and power delivery architectures for advanced memory systems.
What you'll do
- Perform signaling and timing analysis for on-die and off-die interfaces. - Develop and evaluate thermal models to analyze heat transfer and thermal performance. - Analyze power delivery networks (PDNs), including IR-drop, electromigration (EM), and power integrity. - Develop modeling, simulation, and automation tools for power delivery, thermal analysis, and architecture evaluation. - Collaborate with architecture, design, packaging, and technology teams to evaluate system-level trade-offs for HBM technology development.
What you'll need
- 0-2 years of relevant experience in electrical engineering, VLSI design, signal integrity, power integrity, thermal analysis, or semiconductor design. - Currently pursuing a Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field. - Coursework or project experience in analog design, I/O design, signaling, DRAM technologies, high-speed interfaces, packaging, or 2.5D/3D integration technologies. - Understanding of electrical systems, signal integrity, power delivery, circuit analysis, or semiconductor design fundamentals. - Ability to read and interpret technical specifications, datasheets, interface standards, and hardware documentation. - Experience using AI-enabled tools and large language models (LLMs) such as Copilot, Claude, ChatGPT, or similar technologies as part of engineering workflows.
Nice to have
- Familiarity with Cadence EDA tools, MATLAB, thermal analysis tools, or signal integrity tools. - Knowledge of semiconductor packaging, assembly processes, heterogeneous integration, or advanced packaging technologies. - Experience with analog design, I/O design, timing analysis, signal integrity, or system-level electrical modeling. - Experience with thermal modeling, computational analysis, power delivery analysis, IR-drop, electromigration (EM), or power integrity evaluations. - Knowledge of HBM, DRAM, memory interfaces, advanced interconnects, or high-speed signaling technologies. - Experience developing engineering automation tools, simulation environments, data analysis workflows, or modeling frameworks using Python or similar programming languages.
Skills: HBM, signaling and timing analysis, thermal models, power delivery networks, 2.5D/3D integration
This role has been open 4 days — well below the 65-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
303
|
Median days open
65 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (303 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 154 | 303 |
| Median days open | 87 d | 65 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM, signaling and timing analysis, thermal models, power delivery networks, 2.5D/3D integration
Who's hiring in this category
- Micron Technology (this employer) · 153 open roles · median 86 d
- Synopsys · 33 open roles · median 49 d
- Qualcomm · 18 open roles · median 92 d
- Broadcom · 17 open roles · median 50 d
- SanDisk · 17 open roles · median 36 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 303 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.