Intern - Engineer, HIG HBM DTPCO - Richardson, TX, United States
Originally posted 5 October 2026 by the employer.
This role is part of a highly collaborative team focused on advancing High Bandwidth Memory (HBM) solutions.
About the role
This role involves the deep characterization, modeling, and root-cause analysis of High Bandwidth Memory (HBM) solutions. The position focuses on custom bench-level characterization of HBM devices to improve product performance, yield, reliability, and adaptability across future HBM generations.
What you'll do
- Design, build, debug, and complete custom bench-level test setups, fixtures, and measurement flows.
- Perform thermal, mechanical, and electrical characterization of HBM cubes under various stress conditions.
- Develop and maintain Python-, Verilog-, and C/C++-based test programs, stress patterns, workloads, and observability features.
- Analyze MBIST signatures and multifaceted electrical, thermal, and mechanical datasets to identify root causes.
- Leverage AI, Agentic AI, and Generative AI tools to improve engineering workflows and data analysis.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Materials Science, Physics, or a related technical field.
- 3+ years of experience in semiconductor characterization, failure analysis, product engineering, or test engineering.
- Hands-on experience with laboratory equipment such as oscilloscopes, SMUs, power supplies, thermal systems, probe stations, or automated test hardware.
- Programming experience in Python and at least one additional language such as C/C++ or Verilog.
- Experience analyzing complex datasets and driving root-cause investigations using statistical and engineering methods.
Nice to have
- Master's or PhD degree in Electrical Engineering, Computer Engineering, Materials Science, Physics, or a related field.
- Experience with DRAM, HBM, memory subsystems, advanced semiconductor packaging, or silicon characterization.
- Knowledge of thermal, mechanical stress, reliability, yield improvement, DOE methodologies, and power-performance correlation techniques.
- Experience working with MBIST analysis, parametric characterization, failure signatures, and semiconductor test methodologies.
- Proficiency using AI-enabled tools, Agentic AI, Generative AI, or AI-assisted coding platforms.
Skills: custom bench-level test setups, HBM cubes, thermal characterization, MBIST signatures, semiconductor characterization
This role has been open 4 days — well below the 101-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
210
|
Median days open
101 d
|
Median salary
$145k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (210 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 210 |
| Open roles in the wider Silicon Validation & Test family | 211 | 2209 · 111 employers |
| Median days open | 100 d | 101 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $145k |
Skills observed across this category: custom bench-level test setups, HBM cubes, thermal characterization, MBIST signatures, semiconductor characterization
Who's hiring in this category
- Renesas Electronics · 16 open roles · median 91 d
- Teradyne · 15 open roles · median 109 d
- onsemi · 12 open roles · median 112 d
- Qualcomm · 12 open roles · median 115 d
- Infineon Technologies · 9 open roles · median 115 d
- Marvell Technology · 9 open roles · median 106 d
How we counted: 210 open Silicon Test Engineering (Silicon Validation) roles from 58 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.