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Cadence Design Systems

Intern - Characterization and Support (Fall 2026) - San Jose, United States

Cadence Design Systems SAN JOSE, United States Internship 2 months ago
Verification, Validation & Test

$83,200 - $143,520 USD yearly

Originally posted 29 August 2026 by the employer.

Join the Cadence DDR IP group in San Jose.

About the role

This on-site internship focuses on validating system-level and electrical performance of internal silicon test chips within the Cadence DDR IP group.

What you'll do

  • Validate system-level and electrical performance of internal silicon test chips
  • Debug silicon issues in collaboration with analog and digital design teams
  • Deliver high-quality characterization reports
  • Drive system and electrical testing efforts for identifying silicon issues
  • Be involved in debug efforts for identified silicon issues

What you'll need

  • Currently pursuing a Bachelor's or Master’s degree in electrical engineering with 0-2 years of relevant work experience
  • Very good fundamentals in analog and digital electronics
  • Very good fundamentals in RTL
  • Very good fundamentals in Signal integrity
  • Very good fundamentals in control systems
  • Strong analytical and problem-solving skills

Nice to have

  • Prior experience in the hardware semiconductor or electronics industry
  • Experience with script-based test automation in Python
  • Experience with script-based test automation in C
  • Experience with script-based test automation in other scripting tools

Skills: debugging silicon issues, characterization reports, system and electrical testing, test automation, analog and digital electronics

Market context

This role has been open 46 days — slightly above the 41-day median for Post-Silicon Validation roles.

Post-Silicon Validation · Silicon Validation

Open roles in category
412
Median days open
41 d
Median salary
$166k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Cadence Design Systems compares in Post-Silicon Validation hiring
Metric Cadence Design Systems All employers we track in this specialty (412 roles · 61 employers)
Open roles in this specialty 1 412
Open roles in the wider Silicon Validation & Test family 26 2223 · 112 employers
Median days open 46 d 41 d (+5 d vs this employer)
Median salary (USD postings) — $166k

Skills observed across this category: debugging silicon issues, characterization reports, system and electrical testing, test automation, analog and digital electronics

Who's hiring in this category

  • AMD · 58 open roles · median 41 d
  • Micron Technology · 39 open roles · median 37 d
  • Qualcomm · 37 open roles · median 27 d
  • NVIDIA · 25 open roles · median 22 d
  • Graphcore · 21 open roles · median 120 d
  • Microchip Technology · 20 open roles · median 70 d

How we counted: 412 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

Apply now
SAN JOSE, United States
On-site
Internship
$83,200 - $143,520 USD yearly
2 months ago

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