Intern, AI System Architecture Research Scientist

Research memory hierarchies combining HBM, CXL memory, and High Bandwidth Flash for long-horizon agentic AI inference.

Originally posted 11 November 2026 by the employer.

About the role

This internship in the Architecture Research Lab (ARL) explores memory system architectures and optimizations for long-horizon agentic AI and LLM inference. The scope covers system architecture up to the rack level, addressing memory bandwidth and capacity bottlenecks using performance modeling, simulation, and accuracy studies.

What you'll do

• Characterize LLM and agentic inference workloads (multi-turn sessions, long and growing context, reuse across requests) to derive memory capacity, bandwidth, and latency requirements.
• Research memory hierarchies for AI inference combining HBM, near-memory compute, High Bandwidth Flash, and host or CXL memory, analyzing weight and KV cache placement, movement, reuse, and compression.
• Propose hardware features, runtimes, and memory-management policies to maintain long-horizon agent accuracy within memory constraints.
• Build and extend performance models and simulators to conduct design-space explorations across throughput, capacity, and cost metrics.
• Measure the accuracy impact of memory optimizations on long-context and agentic benchmarks using open models.
• Publish research findings, contribute invention disclosures, and help guide future memory product requirements.

What you'll need

• Current enrollment in a PhD program with at least 1 academic quarter or semester remaining.
• Background in AI system architecture and memory systems, including memory hierarchy, DRAM/HBM, and data movement.
• Understanding of LLM and agentic inference (prefill and decode, KV cache, long-context workloads) and the accuracy impacts of optimizations such as KV-cache compression or eviction.
• Experience with performance analysis and modeling of AI systems, including roofline analysis and analytical or simulation-based evaluation.
• Research experience managing model state across memory tiers (KV-cache paging, reuse, offloading, compression, eviction, or weight offloading) in serving stacks such as vLLM, SGLang, or LMCache.
• Strong programming proficiency in Python, C/C++, and experience with PyTorch.

Nice to have

• 3+ years studying toward a PhD in Computer Science.
• Track record as a first author or major contributor on publications at computer architecture, systems, or machine learning venues.

Skills: AI system architecture, memory hierarchy, HBM, LLM inference, performance modeling

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