Interconnect Micro-Architect and Design Development Lead - TX, Austin, United States
Originally posted 21 October 2026 by the employer.
Lead development and execution on the Infinity Fabric Architecture and RTL team for scalable, coherent on-chip interconnects.
About the role
As a senior technical leader on the Infinity Fabric Architecture and RTL team, you will drive the development and execution of key IP within AMD’s scalable, coherent on-chip interconnect. The role combines RTL and microarchitecture expertise with technical leadership across distributed teams supporting CPUs, GPUs, and advanced processor products.
What you'll do
- Drive development and execution across IP component owners, aligning implementation priorities and resolving cross-component dependencies to meet functional, power, performance, area, and timing requirements. - Partner with the IP architect to translate architectural intent into actionable development work, evaluate implementation feasibility, and assess engineering trade-offs. - Lead top-down development scoping for new proposals, advising leadership on execution strategies through data-driven assessments of effort, reuse, dependencies, capacity, and technical risks. - Anticipate execution challenges and direct the engineering response to technical roadblocks, scope changes, and late-discovered bugs. - Drive implementation reviews, technical readiness assessments, and issue closure across component boundaries with verification, physical design, integration, and silicon teams. - Represent the team in design quality and time-to-market improvement initiatives, advancing development processes, methodologies, and tools.
What you'll need
- Background in microprocessor and ASIC development from concept to production, with experience leading engineers through technical expertise. - Hands-on RTL design and microarchitecture expertise to evaluate technical trade-offs across functional, power, performance, area, and timing requirements. - Experience driving complex IP development across globally distributed teams and collaborating with architects, verification, physical design, integration, and silicon teams. - Strong analytical and problem-solving abilities to resolve implementation challenges and support timely, data-driven decisions.
Nice to have
- Industry experience in IP or ASIC design development, with technical leadership across multiple components or engineering teams through silicon delivery. - RTL design and implementation expertise in CPU, GPU, NoC, cache, or related processor subsystems, including strong judgment on power, performance, area, and timing trade-offs. - Understanding of processor and memory-system concepts, including coherency, ordering, and caches. - BS, MS, or PhD degree in Electrical or Computer engineering.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 1051 |
| Open roles in the wider Digital Design & Verification family | 254 | 3283 · 116 employers |
| Median days open | 40 d | 62 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD (this employer) · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.