Integrated Circuit - Packaging Architect Engineer - CA, San Jose, United States
Originally posted 6 August 2026 by the employer.
About the role
This role drives packaging architecture across client, server, gaming, and GPU products. You will collaborate with product design teams and technology development partners to define package roadmaps, architecture, process definitions, and DFM/DFY guidelines.
What you'll do
- Collaborate with product architects in early definition stages to understand and define package architectures and roadmaps. - Lead new package technology development initiatives from concept through full technology qualification. - Drive test vehicle design and manufacturing to establish design rules and DFM/DFY guidelines. - Establish yield roadmaps and lead the implementation of yield and data analytic tools as needed. - Drive technical problem-solving to address yield, reliability, and process development challenges with worldwide ecosystem partners.
What you'll need
- BS, MS, or PhD in Material Science, Mechanical Engineering, Computer Science, Applied Mathematics, Electrical Engineering, or equivalent. - Proven track record of driving technology development in the semiconductor field. - Demonstrated leadership experience directing engineering teams in architecture definition, process definition, or yield improvement.
Nice to have
- Experience in semiconductor technology development roles. - Experience working with manufacturing partners such as suppliers, OSATs, and foundry partners. - In-depth knowledge in material science, thin film process development, and/or packaging. - Experience in a leadership role driving cross-functional teams. - Proven track record of driving yield improvement and defect reduction in a semiconductor fab or packaging environment.
This role has been open 77 days — well below the 115-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
115 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 39 |
| Median days open | 77 d | 115 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Who's hiring in this category
- Marvell Technology · 5 open roles · median 51 d
- Qualcomm · 5 open roles · median 115 d
- Intel Corporation · 4 open roles · median 39 d
- Micron Technology · 4 open roles · median 162 d
- NVIDIA · 4 open roles · median 74 d
- GlobalFoundries · 3 open roles · median 42 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.