Infinity Fabric Senior Staff Pre-Si Verification Engineer - CA, Santa Clara, United States
Originally posted 28 May 2026 by the employer.
Verify configurable switches and die-to-die interconnect within the Infinity Fabric transport layer.
About the role
The Infinity Fabric transport layer verification team is seeking an engineer to verify configurable switches and die-to-die interconnect. Infinity Fabric is deployed across AMD Client, Server, Graphics, and Semi-Custom products.
What you'll do
- Define and drive verification strategy for complex GPU features or subsystems with cross-project and cross-product impact. - Partner with architects, RTL, and firmware leads to influence feature definition, implementation approach, and verification readiness early in the design cycle. - Own verification planning and execution, including risk identification, trade-off analysis, and mitigation strategies. - Lead the development of scalable verification environments using directed and constrained-random testing with SystemVerilog and UVM. - Analyze functional and code coverage at a system level to drive coverage closure strategies across teams. - Mentor and coach junior and senior engineers while driving verification process and workflow improvements.
What you'll need
- Experience in pre-silicon verification, including directed and constrained-random testing. - Experience defining verification strategies, test plans, and coverage closure workflows. - Technical leadership experience coordinating verification efforts and mentoring engineers.
Nice to have
- Proficiency in IP-level ASIC verification and debugging firmware and RTL code using simulation tools. - Proficiency using UVM testbenches and working in Linux and Windows environments. - Experience with Verilog, SystemVerilog, C, and C++. - Experience developing UVM-based verification frameworks, testbenches, processes, and flows. - Experience automating workflows in a distributed compute environment. - Exposure to simulation profiling, efficiency improvement, acceleration, and HLS tools/processes. - Working knowledge of SystemC and TLM. - Scripting language experience in Perl, Ruby, Makefile, or shell. - BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science.
Skills: pre-silicon verification, SystemVerilog, UVM testbenches, ASIC verification, functional coverage
This role has been open 149 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 92 | 1254 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 54 d | 64 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: pre-silicon verification, SystemVerilog, UVM testbenches, ASIC verification, functional coverage
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD (this employer) · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.