[India] Senior UCIe Verification Engineer - Hyderabad Knowledge City, India
Focus on SystemVerilog/UVM verification of UCIe IP and chiplet interconnects.
About the role
This role focuses on SystemVerilog/UVM-based verification of UCIe IP, high-speed interconnects, and SoC subsystems. You will build reusable testbenches, verify protocol compliance, and drive verification closure through tape-out.
What you'll do
- Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration. - Build reusable SystemVerilog/UVM verification environments from scratch, including UVM agents, scoreboards, monitors, protocol checkers, and functional coverage models. - Develop constrained-random and directed test scenarios to verify UCIe protocol features, including link initialization and training, sideband communication, adapter layer, protocol layer, and link power management. - Verify interoperability between UCIe and upper-layer protocols such as PCIe, CXL, or streaming interfaces. - Write and debug SystemVerilog Assertions (SVA) for protocol compliance and interface checks, driving functional and code coverage closure. - Debug RTL, protocol, and testbench issues, and support gate-level simulations, regression execution, and silicon bring-up.
What you'll need
- 6–12 years of experience in functional verification using SystemVerilog and UVM, including building complete UVM environments from scratch. - Hands-on experience in 1–2 successful SoC tape-outs and integrating UCIe subsystems into SoCs. - Technical understanding of UCIe architecture, high-speed serial interfaces, chiplet interconnects, or die-to-die interfaces. - Proficiency with AXI4, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and protocol compliance verification. - Experience writing SystemVerilog Assertions (SVA), gate-level simulation, and waveform analysis. - Experience with scripting languages such as Python, Perl, or Tcl, version control using Git, and emulator-based verification platforms.
Skills: UVM, SystemVerilog, UCIe, protocol compliance, functional coverage
This role has been open 84 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
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Open roles in category
1268
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Median days open
67 d
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Median salary
$185k
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1268 |
| Open roles in the wider Digital Design & Verification family | 8 | 3359 · 116 employers |
| Median days open | 124 d | 67 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, UCIe, protocol compliance, functional coverage
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.