[India] Senior PCIe Verification Engineer - Hyderabad Knowledge City, India
About the role
As a Senior PCIe Verification Engineer on the SoC Verification team, you will develop verification environments, drive verification closure, and ensure first-pass silicon success for PCIe-based subsystems. The role focuses on PCI Express (PCIe) IP and subsystem verification using SystemVerilog and UVM across full SoC integration.
What you'll do
- Develop and execute verification plans for PCIe IPs, subsystems, and SoC integration. - Build reusable SystemVerilog/UVM verification environments from scratch. - Develop constrained-random and directed test scenarios, functional coverage models, assertions, scoreboards, monitors, and protocol checkers. - Verify PCIe functionality across LTSSM, Link Training, Configuration Space, Enumeration, Data Link Layer, Transaction Layer, and PHY interactions, as well as features such as MSI/MSI-X, AER, ASPM, LTR, SR-IOV, ATS, PASID, FLR, and Power Management. - Perform protocol compliance verification using industry-standard PCIe VIPs, alongside RTL, protocol, and UVM testbench debugging. - Support gate-level simulations, regression execution, and post-silicon bring-up activities while collaborating with RTL, architecture, firmware, and validation teams.
What you'll need
- 6–12 years of experience in functional verification using SystemVerilog and UVM. - Strong expertise in PCI Express (PCIe Gen4/Gen5/Gen6) verification and hands-on experience with PCIe Verification IP (VIP). - Solid understanding of PCIe architecture, including Physical Layer, Data Link Layer, Transaction Layer, Configuration Space, LTSSM, and Error Handling and Recovery. - Experience verifying DMA-based PCIe designs, AXI-to-PCIe bridge architectures, and strong knowledge of the AXI4 protocol and SoC interconnects. - Experience writing SystemVerilog Assertions (SVA) with expertise in constrained-random, assertion-based, and coverage-driven verification. - Hands-on experience with 2–3 successful SoC tape-outs, PCIe integration at the SoC level, and gate-level simulations.
Skills: PCIe verification, SystemVerilog/UVM, functional coverage, protocol compliance, SoC tape-outs
This role has been open 103 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
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Open roles in category
1268
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Median days open
67 d
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Median salary
$185k
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1268 |
| Open roles in the wider Digital Design & Verification family | 8 | 3359 · 116 employers |
| Median days open | 124 d | 67 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe verification, SystemVerilog/UVM, functional coverage, protocol compliance, SoC tape-outs
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.