[India] Design Verification Engineer - Hyderabad Knowledge City, India
Dynamic Neural Accelerator AI processor IP verification for AI SoCs.
About the role
This role is part of the Artificial Intelligence Hardware Team at EdgeCortix, working closely with design and architecture teams on IP, performance, and SoC verification. The work focuses on verification environments for AI SoCs incorporating the Dynamic Neural Accelerator AI processor IP.
What you'll do
- Develop verification infrastructure including VIPs, memory models, monitors, and configurable testbenches in SystemVerilog/UVM. - Write, maintain, and debug SystemVerilog assertions. - Develop functional coverage and perform functional and code coverage analysis using coverage-driven verification methodology. - Execute ASIC power estimation and power-aware verification. - Run gate level simulations, delay modeling, and work with emulators. - Automate tool flows and the creation of result reports.
What you'll need
- 6-7 years of experience in functional verification of blocks or systems using SystemVerilog/UVM. - Experience developing full verification infrastructure from scratch and applying constraint random verification. - Experience verifying systems involving high-speed buses such as AXI4. - Verification experience with PCIe, DDR, UCIe, Ethernet, or RISC-based CPUs. - Working knowledge of emulator-based verification, gate level simulations, and delay modeling. - Strong experience debugging RTL and testbenches.
Nice to have
- Prior experience working with VIPs and verification environments that involve VIPs. - Prior experience verifying IPs or systems that include PCI-E or DDR protocols. - Experience with SoC level verification. - Experience using Continuous Integration tools such as Jenkins, Gitlab CI, or Circle CI. - Experience with formal verification techniques. - Experience with scripting languages such as Perl or Python.
Skills: SystemVerilog/UVM, functional verification, gate level simulation, power-aware verification, assertions
This role has been open 124 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1268 |
| Open roles in the wider Digital Design & Verification family | 8 | 3359 · 116 employers |
| Median days open | 124 d | 67 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog/UVM, functional verification, gate level simulation, power-aware verification, assertions
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.