$143,800 - $230,000 USD yearly
Originally posted 22 September 2026 by the employer.
Develop scalable testbench environments and drive verification for designs featuring PCI Express.
About the role
This role involves architecting and developing scalable testbench environments and driving verification closure for Block/Core/SOC designs with a focus on PCI Express.
What you'll do
- Architect and develop scalable and reusable Testbench environment using verification methodologies.
- Drive Test plans for all features for Block/Core/SOC and write Functional coverage.
- Build pseudo-random tests to verify and achieve full Functional coverage.
- Debug Regression failures, analyze Functional Coverage gaps, and improve tests.
- Guide and mentor junior team members.
- Lead documentation of verification strategy and conduct reviews with design/architecture.
What you'll need
- Bachelor’s degree in Electrical/Electronics/Equivalent with 12+ years of relevant experience; or Master’s degree in Electrical/Electronics/Equivalent with 10+ years of relevant experience.
- 10+ years of experience in developing complex Verification Environments, Test plans, Functional coverage, and pseudo-random testing.
- Experience with a full ASIC cycle from Architecture development to Tapeout, with a focus on Verification.
- Proficiency in System Verilog and Verification Methodologies like UVM/VMM.
- Debug skills in analyzing regression failures and understanding complex designs.
- Understanding of a complex protocol like PCI Express or other multi-layered protocols.
Nice to have
- Experience in PCIe protocol.
- Comfort with Makefiles.
- Experience with verifying other protocols like AXI.
Skills: Testbench environment, UVM/VMM, System Verilog, Functional coverage, pseudo-random testing
This role has been open 19 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1183
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1183 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 1183 |
| Open roles in the wider Digital Design & Verification family | 48 | 3171 · 114 employers |
| Median days open | 90 d | 64 d (+26 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Testbench environment, UVM/VMM, System Verilog, Functional coverage, pseudo-random testing
Who's hiring in this category
- Qualcomm · 105 open roles · median 44 d
- AMD · 102 open roles · median 51 d
- NVIDIA · 73 open roles · median 65 d
- Synopsys · 61 open roles · median 27 d
- SiFive · 54 open roles · median 68 d
- Cadence Design Systems · 51 open roles · median 110 d
How we counted: 1183 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.