IC RTL2GDS Architect, AE - San Jose, United States
$157,500 - $292,500 USD yearly
Originally posted 24 July 2026 by the employer.
Guide customer digital implementation and signoff flows across advanced nodes at 3nm and below.
About the role
The Architect serves as a technical leader within Cadence’s North America Field Applications Team, guiding strategic customer engagements and implementation of EDA and Agentic-AI solutions. The scope centers on digital implementation and signoff technologies across advanced nodes at 3nm and below.
What you'll do
- Lead customer engagements to optimize PPA, driving adoption of digital implementation, signoff technologies, and Agentic-AI features across nodes at 3nm and below. - Partner with R&D and Product Engineering to influence tool enhancements based on customer requirements. - Execute benchmarks, flow optimizations, and methodology deployments for Synthesis, P&R, STA, IR Drop, and power/timing closure. - Represent Cadence at industry forums, author technical papers, and deliver presentations.
What you'll need
- 15+ years of experience in IC design implementation and signoff, with success managing large-scale technical programs. - BS or MS in Electrical Engineering, Computer Engineering, or a related field. - Expertise in digital design fundamentals, advanced node implementation at 3nm and below, and EDA tool ecosystems. - Track record of leading technical teams and driving customer engagements. - Proficiency in scripting with Tcl, Python, or Perl for flow customization and design closure.
Nice to have
- Prior experience with Cadence tools including Genus, Innovus, Tempus, Voltus, Conformal, and Cerebrus, or competitive solutions.
Skills: IC design implementation, signoff, PPA, Cadence tools, RTL2GDS, Tcl/Python/Perl scripting
This role has been open 215 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 156 | 704 |
| Open roles in the wider Physical Implementation family | 182 | 1513 · 111 employers |
| Median days open | 152 d | 70 d (+82 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: IC design implementation, signoff, PPA, Cadence tools, RTL2GDS, Tcl/Python/Perl scripting
Who's hiring in this category
- Cadence Design Systems (this employer) · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology · 45 open roles · median 55 d
- GlobalFoundries · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.