IC/RTL Design Engineer - San Jose, United States
Originally posted 6 July 2026 by the employer.
This role focuses on digital front-end RTL at the heart of the chip, including the high-speed datapath that moves data between UCIe and the optical front end.
About the role
This role involves designing and implementing the digital front-end RTL at the heart of the chip, including the high-speed datapath that moves data between UCIe and the optical front end.
What you'll do
- Develop block-level micro-architecture and contribute to interface and register definitions.
- Design and implement front-end RTL blocks in SystemVerilog, including datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
- Integrate IP and support parameterization for configurability.
- Write lint-clean, CDC/RDC-clean RTL that follows coding and quality standards.
- Write block-level testbenches, sanity checks, and assertions (SVA) for blocks before handoff to DV.
- Design for power and timing, managing block activity, clock-gating, pipelining, and retiming, and partner with the backend team on physical closure.
- Debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks.
What you'll need
- BS or MS in Electrical/Computer Engineering (or equivalent experience).
- 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
- Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
- Lint and CDC/RDC discipline and clean-RTL practices.
- Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.
- Strong debug skills in simulation; scripting in Python, Perl, or TCL.
Nice to have
- High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).
- FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
- Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.
- Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.
- Low-power / UPF and DFT (scan) concepts.
- Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.
This role has been open 73 days — well above the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1037
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (1037 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1037 |
| Open roles in the wider Digital Design & Verification family | 8 | 3201 · 115 employers |
| Median days open | 73 d | 60 d (+13 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 64 d
- Synopsys · 86 open roles · median 32 d
- AMD · 71 open roles · median 38 d
- Analog Devices · 47 open roles · median 50 d
- NVIDIA · 44 open roles · median 60 d
- NXP Semiconductors · 42 open roles · median 86 d
How we counted: 1037 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.