IC Package FEA Engineer - San Jose, United States
Originally posted 22 March 2026 by the employer.
About the role
You will work hands-on with emerging packaging and photonic-integration technologies, including co-packaged fiber-optic transceivers, novel optical connectors, and complex chip-stacking approaches such as 3DIC, hybrid copper bonding, and heterogeneous integration.
What you'll do
- Perform FEA simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across advanced package architectures (flip-chip, fan-out, 2.5D/3D IC, chiplet-based, TSVs).
- Define simulation requirements, analyse results, and deliver actionable design and process recommendations.
- Support technology road mapping by assessing new materials, interconnect structures, and process flows from a thermo-mechanical reliability perspective.
- Lead DOE studies and sensitivity analyses to identify key reliability and performance drivers.
- Collaborate with cross-functional teams (design, photonics, manufacturing, reliability, vendors) to ensure robust, scalable package architectures.
What you'll need
- Bachelor’s in Mechanical Engineering (or related field) with 12+ years FEA experience, Master’s with 10+, or PhD with 7+.
- Deep expertise in advanced packaging technologies, including flip-chip, FOWLP, 2.5D/3D integration, chiplet architectures, and TSVs.
- Strong understanding of materials behavior across polymers, metals, ceramics, and their thermo-mechanical interactions.
- Familiarity with semiconductor packaging processes such as die attach, underfill, molding, bumping, and reflow.
- Proficiency with FEA tools, including Ansys Classic/Mechanical and Abaqus.
- Ability to interpret and correlate complex simulation results using first-principles mechanical engineering concepts.
- Demonstrated experience calibrating models with empirical data, including hands-on mechanical testing and metrology.
- Proven capability in developing and running lab-level experiments to validate simulations and identify root causes.
This role has been open 73 days — well above the 62-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
299
|
Median days open
62 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (299 roles · 59 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 299 |
| Open roles in the wider Process, Fab & Equipment family | 49 | 9897 · 109 employers |
| Median days open | 72 d | 62 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Who's hiring in this category
- KLA Corporation · 43 open roles · median 129 d
- Micron Technology · 38 open roles · median 38 d
- Renesas Electronics · 17 open roles · median 48 d
- Intel Corporation · 16 open roles · median 42 d
- GlobalFoundries · 14 open roles · median 61 d
- Infineon Technologies · 14 open roles · median 67 d
How we counted: 299 open Packaging Engineering (Advanced Packaging) roles from 59 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.