IC Layout Engineer – Optical Engine Silicon - Singapore

Originally posted 24 September 2026 by the employer.

About the role

This role involves owning the layout for electronic ICs (EICs) and photonic ICs (PICs) for optical interconnects. The position focuses on high-speed analog blocks where parasitic effects, return paths, and current density are critical to performance.

What you'll do

• Own layout for assigned analog and mixed-signal blocks from floorplan through clean sign-off, including device placement, matching, symmetry, shielding, guard rings, and routing.
• Execute parasitic-aware layout, incorporating designer constraints, running extraction, and communicating results.
• Route high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures.
• Run and close DRC, LVS, antenna, and density checks, and support electromigration and IR drop analysis.
• Support top-level assembly and chip finishing activities through tape out.
• Support PIC layout as needed, including waveguide and curvilinear structures, bends, tapers, couplers, and modulator/photodetector electrodes.
• Run photonics-specific verification, including curvilinear DRC, waveguide connectivity checks, LVS on custom photonic cells, and GDS stream-out.
• Develop scripts and reusable structures to enhance layout team efficiency.

What you'll need

• Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
• 1–3 years in custom analog, RF, or mixed-signal IC layout, with at least one tapeout to silicon.
• Solid working experience with Cadence Virtuoso, including Layout XL and constraint-driven flows.
• Practical parasitic awareness, understanding matched pair drawing and critical nets.
• Fundamentals in electromigration and IR drop, including current density limits, power routing, and relevant checks.
• Fundamentals in electromagnetics for on-chip structures, covering coupling, shielding, and high-speed routing constraints.
• Physical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
• Scripting for layout automation using SKILL, Python, or both.

Nice to have

• SiGe BiCMOS layout experience and associated passive/isolation practices.
• Advanced FinFET CMOS layout at 7nm and below, including multi-patterning, coloring, fin/poly grid constraints, and DRC complexity.
• Photonic IC layout exposure, including waveguide routing, curvilinear geometry, and photonics PDK design rules.
• Experience with parametric photonic cells (PCells) in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS), curvilinear-to-grid snapping, and fracture rules.
• Familiarity with silicon photonics building blocks and their layout sensitivities: Mach-Zehnder and ring modulators, Ge photodetectors, thermal phase shifters, and fiber coupling structures.
• Exposure to 2.5D and 3D integration, interposers, or micro-bump and copper pillar arrays.
• Layout on optical front ends: TIA, modulator driver, or high-speed serial link blocks.

Skills: Cadence Virtuoso, DRC, LVS, PIC layout, waveguide, parasitic-aware layout