IC Layout Engineer - Singapore-Yishun, Singapore
Originally posted 30 July 2026 by the employer.
Design high-quality layouts across Standard Cells and Mixed-Signal IP.
About the role
This role is responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules.
What you'll do
- Apply design guidelines and advanced process rules to deliver robust layouts.
- Manage schedule and execute layouts from the transistor level up, including cell- and block-level floorplanning.
- Adopt new methodologies and communicate actively across sites.
- Work closely with senior layout engineers.
What you'll need
- Bachelor’s Degree in Electronic Engineering.
- 2 to 3 years of hands-on IC layout experience.
- Solid grasp of Standard Cell, Memory, or Analog/Mixed-Signal layout basics.
- Familiarity with basic ESD/Latch-up layout techniques and transistor-level placement.
- Practical experience with physical verification: DRC, LVS, ERC, and Antenna checks.
- Basic understanding or exposure to sub-micron or advanced process nodes (e.g., 5nm, 3nm, 2nm, 1.4nm).
- Proficiency with Cadence Virtuoso layout tool.
- Proficiency with Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis).
Nice to have
- Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming.
Skills: IC layout, Standard Cells, Mixed-Signal IP, Cadence Virtuoso, Calibre
This role has been open 61 days — well above the 25-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
49
|
Median days open
25 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 49 |
| Open roles in the wider Analog & Mixed-Signal family | 42 | 1385 · 108 employers |
| Median days open | 8 d | 25 d (−17 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: IC layout, Standard Cells, Mixed-Signal IP, Cadence Virtuoso, Calibre
Who's hiring in this category
- Celero · 8 open roles · median 32 d
- Analog Devices · 7 open roles · median 12 d
- Marvell Technology · 4 open roles · median 16 d
- Broadcom (this employer) · 3 open roles · median 8 d
- onsemi · 3 open roles · median 35 d
- QORVO · 3 open roles · median 33 d
How we counted: 49 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.