IC Design Verification Engineer - San Jose, United States
Originally posted 6 July 2026 by the employer.
This role involves verifying blocks and subsystems of a first-of-its-kind chiplet.
About the role
You will verify the blocks and subsystems of a first-of-its-kind chiplet, building UVM testbenches, writing tests, and driving coverage to closure.
What you'll do
- Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
- Write directed and constrained-random tests; develop functional coverage and drive it to closure.
- Verify the in-house engines against an algorithmic golden model.
- Integrate and use VIP (e.g., UCIe) and run compliance, link-training, loopback, and lane-repair scenarios.
- Run regressions, triage failures, and help maintain the CI/regression flow.
- Participate in gate-level and low-power (UPF) verification during signoff.
What you'll need
- BS or MS in Electrical/Computer Engineering (or equivalent experience).
- 3+ years of ASIC/SoC functional verification.
- Solid UVM/SystemVerilog; constrained-random and coverage-driven verification.
- Testbench development and coverage closure.
- Strong debug skills across simulation; scripting in Python, Perl, or TCL.
- Familiarity with regression/CI flows and failure triage.
Nice to have
- High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification.
- UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience.
- Mixed-signal verification (Verilog-AMS or SV real-number models).
- Hardware-assisted verification — emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
- Low-power/UPF and gate-level simulation; performance-verification methodology.
- Exposure to NICs, Ethernet/IB switches, or cache-coherent fabrics.
- Formal verification for control/interlock logic; portable stimulus.
Skills: UVM, SystemVerilog, constrained-random, coverage closure, ASIC functional verification, testbench development
This role has been open 73 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1202 |
| Open roles in the wider Digital Design & Verification family | 8 | 3201 · 115 employers |
| Median days open | 73 d | 65 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, constrained-random, coverage closure, ASIC functional verification, testbench development
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.