HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)
$115,600 - $173,400 USD yearly
Originally posted 17 December 2025 by the employer. Relisted by the employer on 26 October 2026.
About the role
This role involves architecting and implementing low-skew, power-efficient clock distribution networks and driving physical design through RTL-to-GDSII flow for complex designs. Work is conducted full-time onsite in San Diego, CA (5 days per week) and requires US Citizenship and eligibility for a U.S. Government security clearance.
What you'll do
- Execute floorplanning, placement, clock tree synthesis (CTS), and routing using tools such as Innovus and ICC2. - Drive static timing analysis (STA) and timing closure across multiple corners and modes using PrimeTime or Tempus, including SDC timing constraint management. - Conduct full-chip and block-level physical verification, resolving DRC, LVS, ERC, antenna, and density violations using Calibre, Pegasus, or ICV. - Implement low-power design architectures using CLP methodology, UPF/CPF power intent files, power gating, and level shifters. - Support tapeout readiness through formal equivalence checks, GDS-to-GDS comparisons, multi-corner/multi-mode signoff, and EM/IR analysis. - Build and maintain flow automation scripts using TCL, Python, and Perl.
What you'll need
- Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design/integration experience, Master's with 1+ year, or a PhD. - 3 years of physical design experience with a focus on clock tree design and implementation. - Hands-on experience with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). - Experience with advanced FinFET nodes (e.g., 7nm, 5nm, 3nm). - Proficiency in scripting with TCL, Python, or Perl for reference flow automation. - U.S. Citizenship and eligibility to receive a U.S. Government security clearance.
Nice to have
- Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies. - Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling. - Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe). - Understanding of package-level clock planning and signal integrity.
Skills: RTL-to-GDSII flow, Floor-planning, Clock Tree Synthesis, Place-n-Route, DRC, Timing closure
This role has been open 201 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
676
|
Median days open
66 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (676 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 126 | 676 |
| Open roles in the wider Physical Implementation family | 173 | 1513 · 111 employers |
| Median days open | 49 d | 66 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: RTL-to-GDSII flow, Floor-planning, Clock Tree Synthesis, Place-n-Route, DRC, Timing closure
Who's hiring in this category
- Qualcomm (this employer) · 123 open roles · median 49 d
- AMD · 63 open roles · median 28 d
- Intel Corporation · 40 open roles · median 18 d
- Synopsys · 37 open roles · median 40 d
- NVIDIA · 36 open roles · median 68 d
- Broadcom · 35 open roles · median 105 d
How we counted: 676 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.