HSIO Validation Lead – Silicon Co-Design - CA, Santa Clara, United States
Originally posted 27 July 2026 by the employer.
Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces.
About the role
This role involves validating high-speed input/output (HSIO) interfaces and working on silicon co-design at the boundary between design and physical implementation.
What you'll do
- Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces.
- Drive root cause analysis across protocol behavior, signal integrity, firmware/driver interactions, platform topology, and silicon marginalities.
- Define validation strategy, including test coverage, debug priorities, margining methodology, and stress criteria.
- Build and deploy AI agents for automated debug triage, intelligent data pipelines, and analysis flows.
- Ensure robust interoperability across the full ecosystem, including retimers, switches, accelerators, CPUs, GPUs, and multi-device system topologies.
- Translate insights from real silicon into methodology and coverage improvements for future products.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
- 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on hardware.
- Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
- Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board/system interactions.
- Hands-on lab depth with oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools.
- Ability to debug across the full stack, including hardware, firmware, drivers, and platform design.
This role has been open 82 days — well below the 110-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
197
|
Median days open
110 d
|
Median salary
$140k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (197 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 197 |
| Open roles in the wider Silicon Validation & Test family | 97 | 2219 · 113 employers |
| Median days open | 82 d | 110 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $140k |
Who's hiring in this category
- Renesas Electronics · 13 open roles · median 100 d
- Teradyne · 13 open roles · median 118 d
- Qualcomm · 11 open roles · median 111 d
- onsemi · 10 open roles · median 133 d
- Infineon Technologies · 9 open roles · median 115 d
- Marvell Technology · 9 open roles · median 115 d
How we counted: 197 open Silicon Test Engineering (Silicon Validation) roles from 58 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.