High Speed PHY FW Engineer - San Jose, United States
$101,500 - $188,500 USD yearly
Originally posted 13 July 2026 by the employer.
About the role
Cadence Design Systems is seeking a High Speed PHY FW Engineer to contribute across all phases of firmware development for high speed SERDES. The role spans architecture development, implementation, verification simulations, post-silicon testing, and customer deployment for physical IP serial-link protocols.
What you'll do
- Contribute to firmware architecture development and implement defined firmware features for high speed SERDES. - Work closely with verification teams to debug and fix firmware issues discovered during verification simulations. - Participate in post-silicon testing and validation to identify firmware and hardware functionality and performance issues, implementing needed firmware improvements. - Build system-level prototype control software to develop and validate adaptation, equalization, and control algorithms for high speed SERDES. - Support validation teams during electrical and system characterization. - Interact with Product Engineering, System Validation, and Design teams to debug IP issues in the field, provide hot fixes, and support customer IP deployment.
What you'll need
- BSc or MSc in Electrical Engineering. - Solid programming knowledge in C/C++ and Python. - Understanding of wireline communication principles. - Knowledge in mixed signal circuit design and digital signal processing techniques. - US Citizenship or Permanent Residency.
Skills: firmware, high speed SERDES, post-silicon testing, C/C++, wireline communication