High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei) - Hsinchu City, Taiwan

Originally posted 20 March 2026 by the employer — open 174 days.

This role focuses on the integration and performance evaluation of 3rd party IPs such as USB and PCIe.

About the role

This role involves architecting and implementing RTL designs for complex SoC platforms, with a focus on integration and performance evaluation of 3rd party IPs such as USB and PCIe.

What you'll do

• Define and implement RTL architecture for SoC subsystems.
• Integrate 3rd party IPs (USB, PCIe, UHS) into SoC designs and evaluate their performance.
• Develop and optimize RTL code for performance, power, and area efficiency.
• Collaborate with verification teams to ensure functional correctness and coverage.
• Work with physical design teams to achieve timing closure and DFT compliance.
• Debug and resolve RTL issues across simulation, emulation, and silicon validation.

What you'll need

• Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of hands-on experience in RTL design and SoC integration.
• Proficiency in Verilog/SystemVerilog and RTL design methodologies.
• Experience with integration and performance evaluation of USB / PCIe / UHS 3rd party IPs.
• Familiarity with RTL-to-GDSII flow and timing closure.
• Strong scripting skills in Python, Tcl, or Shell.
• Excellent problem-solving skills.

Nice to have

• Experience with low-power design techniques and clock/power domain crossing.
• Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design.
• Familiarity with post-silicon validation and debug of interface IPs.
• Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools.
• Experience correlating pre-silicon verification with post-silicon performance/yield.

Skills: RTL architecture, USB, PCIe, UHS, RTL-to-GDSII flow, timing closure