High-Speed IO Architect - Digital - PCIe/UCIe/Ethernet Subsystems - San Jose, CA
About the role
This role involves owning the high-speed interface architecture across various product families, driving decisions from SerDes architecture to UCIe die-to-die integration. This position focuses on defining the architecture, validating tradeoffs, and guiding execution through tape-out for high-speed interfaces like PCIe, UCIe, and Ethernet Subsystems.
What you'll do
- Define high-speed IO architecture for PCIe/Ethernet-224G/448G scale-up fabric/CPO-optics to electrical interfaces.
- Define die-to-die interface architecture for UCIe integration, including flit formats, credit-based flow control, sideband management, and latency targets.
- Architect the SerDes-to-photonics interface, retimer integration, and co-packaged optics (CPO) readiness.
- Own the signal integrity budget: TX/RX equalization, channel loss allocation, crosstalk margins, and jitter decomposition.
- Guide SerDes PHY selection and evaluation, assessing vendor IP and establishing integration requirements.
- Define and review UCIe PHY integration, including bump map, power domain partitioning, analog/digital co-design requirements, and pad ring architecture.
- Collaborate on protocol bridge design for PCIe TLP ↔ UCIe flit conversion, flow control, and error handling.
- Drive DFT and compliance test architecture for PCIe certification and UCIe conformance testing.
- Establish PVT margin strategies and power management per-lane DVFS, shutdown sequences, and IVR chiplet coordination.
What you'll need
- 15+ years in high-speed interface architecture.
- Deep expertise in PCIe architecture from PHY layer through controller and protocol stack, with direct tape-out experience.
- UCIe standard familiarity, including flit-based transport, sideband protocol, and die-to-die integration in 2.5D/3D packages.
- Signal integrity expertise: S-parameter analysis, channel simulation (HSPICE/IBIS-AMI), eye diagram closure, and crosstalk budgeting.
- Experience with advanced nodes and advanced packaging (CoWoS, EMIB, InFO).
- Track record of driving complex multi-party IP integrations from architecture through tape-out.
Nice to have
- Experience with 224G/400G+ SerDes architectures for scale-up AI fabric (NVLink, UALink, Ultra Ethernet, or proprietary).
- Familiarity with electrical-optical co-design for CPO or near-package optics; EIC retimer or photonic interface experience.
- Prior work in chiplet-based multi-die architectures, including bumping strategy, KGD handling, and heterogeneous integration.
- PCIe-SIG membership or active contribution to UCIe Consortium working groups.
Skills: High-Speed IO Architect, PCIe, UCIe, Ethernet Subsystems, PHY integration, Signal integrity
This role has been open 49 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
76 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (244 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1419 · 106 employers |
| Median days open | 49 d | 76 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: High-Speed IO Architect, PCIe, UCIe, Ethernet Subsystems, PHY integration, Signal integrity
Who's hiring in this category
- AMD · 32 open roles · median 36 d
- Synopsys · 29 open roles · median 24 d
- Cadence Design Systems · 19 open roles · median 182 d
- Qualcomm · 18 open roles · median 60 d
- Micron Technology · 13 open roles · median 69 d
- Apple · 12 open roles · median 10 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.