High-speed Electrical/Optical Post-Silicon Engineer
$192,000 - $288,000 USD yearly
Originally posted 21 August 2026 by the employer.
Drive hands-on measurements, validation, and debug of 224G/448G electrical and optical interconnects.
About the role
The scope includes channel characterization, passive measurements, SerDes validation, PDN debug, and SW/HLOS-driven system validation.
What you'll do
- Plan and drive 224G/448G electrical/optical measurements and channel characterization across package, PCB, connector, cable, optical module, and system channels.
- Analyze S-parameters, loss, impedance, skew, crosstalk, jitter/noise, reflections, eye margin, and link robustness.
- Lead bring-up, characterization, margining, shmoo, stress, and compliance-readiness across reference boards, optical modules, retimers, and active/passive cables.
- Drive PDN measurement and failure isolation across self-noise, coupling, rail droop/ripple, sequencing, and package/board power delivery.
- Develop automation, data reduction scripts, dashboards, regression flows, and stress content.
- Work with SerDes PHY, SIPI/PDN, package, PCB, optics, firmware, software, and validation teams to drive closure.
What you'll need
- 8 years of relevant experience in post-silicon, SI/PI, SerDes/DDR, optical, package/PCB, or system validation.
- Strong fundamentals in high-speed digital design, SerDes/DDR PHYs, SI/PI, transmission lines, jitter/noise, equalization, channel modeling, and measurement correlation.
- Hands-on experience with VNAs, oscilloscopes, BERTs, TDR/TDT, rail probing, spectrum analyzers, optical BER/power test equipment, and precision probing/fixturing.
- Experience validating and debugging high-speed links such as DDR, PCIe/CXL, Ethernet, UCIe/chip-to-chip, optical module interfaces, or retimers.
- Strong PDN/system debug experience, including rail noise/ripple, droop/coupling, sequencing, and package/board PDN behavior.
Nice to have
- Experience with 112G/224G/448G-class SerDes, PAM4/PAM6/PAM8 signaling, DSP-based SerDes, optical module host interfaces, and advanced equalization/calibration.
- Experience with IEEE Ethernet, DDR, PCIe/CXL, UCIe, or similar high-speed electrical/optical standards and debug methodologies.
- Experience with optical/electrical co-validation, module bring-up, optical link debug, electrical-to-optical correlation, retimer/re-driver tuning, and link budget closure.
- Experience with package/PCB test vehicles, socketed and solder-down platforms, passive/active measurements, and DOE-based characterization.
- Experience driving complex customer, supplier, or platform escalations where root cause spans silicon, package, board, firmware, software, thermal, and system conditions.
- Familiarity with Linux, UEFI, HLOS validation, embedded instrumentation, telemetry collection, and stress workloads.
This role has been open 55 days — below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 118 |
| Open roles in the wider Silicon Validation & Test family | 131 | 2216 · 112 employers |
| Median days open | 37 d | 64 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm (this employer) · 19 open roles · median 37 d
- AMD · 15 open roles · median 63 d
- NVIDIA · 15 open roles · median 70 d
- Graphcore · 10 open roles · median 121 d
- Amazon · 6 open roles · median 40 d
- Micron Technology · 5 open roles · median 211 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.